Enhanced VSB Viterbi decoder

ABSTRACT

An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbi decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation reissue application of U.S. Reissueapplication Ser. No. 14/206,939, filed on Mar. 12, 2014, currentlypending, which is a reissue application of U.S. Pat. No. 8,135,095 B2,issued from U.S. patent application Ser. No. 12/824,078, filed on Jun.25, 2010, which is a continuation of U.S. application Ser. No.11/273,854, filed Nov. 14, 2005, now U.S. Pat. No. 7,933,365, whichclaims the benefit of earlier filing date and right of priority toKorean Patent Application No. 10-2005-0001829, filed on Jan. 7, 2005,and Korean Patent Application No. 10-2004-0093567, filed on Nov. 16,2004, the contents of which are all hereby incorporated by reference asif fully set forth herein in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an enhanced 8 vestigial sideband(E8-VSB) receiver, which can receive a plurality of sets of enhanceddata, each set of data being encoded by a different code rate, and moreparticularly, to a VSB receiver having an enhanced Viterbi decoder.

2. Discussion of the Related Art

Since the second half of 1998, the United States of America has adoptedan advanced television systems committee (ATSC) 8 vestigial sideband(VSB) transmission method as the 1995 standard for broadcasting.Presently, the Republic of Korea is also providing broadcast programs byadopting the ATSC 8VSB transmission method as the standard forbroadcasting. Such ATSC 8VSB transmission method has been establishedfor the essential purpose of high definition imaging.

However, a system that may deteriorate the picture quality, yet stablyreceive incoming images, or a transmission standard for a systemenabling data to be received with more stability as compared to videosignals, due to the contents of the data, has also been on demand in theATSC 8VSB transmission method. In addition, such additional transmissionstandards are to be regulated within the scope of not affecting thesystem for receiving the conventional ATSC 8VSB signal. And, also, thereceiver of a newly established standard is regulated to be able toreceive both the conventional ATSC 8VSB signal and the enhanced 8-VSB(hereinafter referred to as E8-VSB) signal. Accordingly, the E8-VSBsystem adopts the conventional 8VSB system and adds new types ofservices, which enable more enhanced reception of signals to beperformed. Furthermore, due to the newly added services, theconventional services are also enabled to perform stable receivingfunctions.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an enhanced 8vestigial sideband (E8-VSB) Viterbi decoder that substantially obviatesone or more problems due to limitations and disadvantages of the relatedart.

An object of the present invention is to provide an enhanced 8 vestigialsideband (E8-VSB) Viterbi decoder that can perform a Viterbi decoding ofan enhanced symbol and a main symbol in an E8-VSB receiving system.

Another object of the present invention is to provide an enhanced 8vestigial sideband (E8-VSB) Viterbi decoder that can perform a Viterbidecoding of only an enhanced symbol in an E8-VSB receiving system.

Additional advantages, objects, and features of the invention will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objectives and other advantages of the invention may berealized and attained by the structure particularly pointed out in thewritten description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, thepresent invention provides a vestigial sideband (VSB) receiver and amethod of decoding a digital broadcast signal in the VSB receiver. TheVSB receiver includes a tuner for tuning an RF broadcast signal andconverting the RF signal into an IF signal, and an IF mixer forconverting the IF signal into a baseband signal, and a demodulator fordemodulating the baseband signal to a VSB signal, and an enhancedequalizer for compensating channel distortion of the VSB signal andoutputting an equalized symbol. The VSB receiver further includes anenhanced Viterbi decoder for estimating whether polarity inversionoccurred during a symbol period of the equalized symbol andViterbi-decoding the equalized symbol based on the polarity estimation.

The VSB decoder includes a first accumulate/compare/select (ACS) unitand a second ACS unit. The first ACS unit performs ACS operation for aninput symbol assuming that polarity inversion did not occur during asymbol period of the input symbol. On the other hand, the second ACSunit performs ACS operation assuming that polarity inversion did occurduring the symbol period. The VSB Viterbi decoder further includes apolarity inversion estimator which estimates polarity of the inputsymbol, a first path history unit for keeping track of a first pathhistory of the input symbol by saving symbol survivors received from thefirst ACS unit, and a second path history unit for keeping track of asecond path history of the input symbol by saving symbol survivorsreceived from the second ACS unit. Finally, the VSB Viterbi decoderincludes a decision selection unit for selecting one of decisionsoutputted from the first and second path history unit based on theestimated polarity.

The VSB Viterbi decoder further includes a branch metric calculator forcalculating branch metrics of the input symbol corresponding to 8 levelsand outputting the branch metrics to the first and second ACS units. Inone example, the VSB Viterbi decoder may further include a post decoderfor post-decoding a C2 bit of the selected decision, and a multiplexerwhich outputs an X2 bit of the selected decision as an upper bit andoutputs a dummy bit as a lower bit when the input symbol is an enhancedsymbol. The multiplexer outputs an X1 bit of the selected decision as alower bit and outputs the post-decoded C2 bit as a upper bit if theinput symbol is a main symbol. In alternative example, the VSB Viterbidecoder may further include a symbol re-ordering unit for re-orderingthe selected decision by 12-way symbol de-interleaving simultaneously.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate embodiments of the invention andtogether with the description serve to explain the principle of theinvention.

In the Drawings:

FIG. 1 illustrates a block diagram showing a structure of an E8-VSBtransmitting system according to the present invention;

FIG. 2 illustrates a block diagram showing a structure of an E8-VSBreceiving system according to the present invention;

FIG. 3 illustrates a detailed block diagram of an enhanced channeldecoder and a demultiplexer shown in FIG. 2;

FIG. 4A illustrates a detailed block diagram of an E8-VSB convolutionencoder shown in FIG. 1;

FIG. 4B illustrates a detailed block diagram of an enhanced symbolprocessor shown in FIG. 4A;

FIG. 4C illustrates a detailed block diagram showing a data flow, when asymbol inputted to the enhanced symbol processor of FIG. 4B is a mainsymbol;

FIG. 4D illustrates a detailed block diagram of a data flow, when asymbol inputted to the enhanced symbol processor of

FIG. 4B is an enhanced symbol;

FIG. 5A illustrates an enhanced symbol processor and a trellis encoderfor processing a main symbol;

FIG. 5B illustrates an enhanced symbol processor and a trellis encoderfor processing an enhanced symbol;

FIG. 5C illustrates an enhanced symbol processor and a trellis encoderprocessing an enhanced symbol, where the functions of a post decoder anda pre-coder are canceled out;

FIG. 6 illustrates a state transition diagram of the enhanced symbol andthe main symbol;

FIG. 7A illustrates a state transition diagram of a ¼ enhanced symbol,when repeated ¼ symbols are identical to one another;

FIG. 7B illustrates a state transition diagram of a ¼ enhanced symbol,when repeated ¼ symbols are different from one another;

FIG. 8 illustrates an example of a polarity inversion in the enhancedsymbol;

FIG. 9 illustrates an example of a path metric calculation process ofthe enhanced symbol and the main symbol;

FIG. 10 illustrates examples (a) to (e) of control signals beinginputted to the E8-VSB Viterbi decoder;

FIG. 11 illustrates an enhanced/main integrated Viterbi decoderaccording to a first embodiment of the present invention;

FIG. 12 illustrates a state transition diagram of an enhanced symbolbeing interrupted by a main symbol;

FIG. 13 illustrates examples (a) to (c) of an input column and an outputcolumn of the Viterbi decoder;

FIG. 14 illustrates a re-ordering of the enhanced symbol; and

FIG. 15 illustrates an enhanced-only Viterbi decoder according to asecond embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers will be usedthroughout the drawings to refer to the same or like parts.

A general structure of an E8-VSB standard receiver and transmitter aredisclosed herein. More specifically, FIG. 1 illustrates a block diagramof an E8-VSB transmitting system according to the present invention, andFIG. 2 illustrates a block diagram of an E8-VSB receiving systemaccording to the present invention. More specifically, the E8-VSBtransmitting system may transmit MPEG-4 images that are currently beingused extensively or other diverse additional data (i.e., programexecution file, stock information, etc.). The E8-VSB transmitting systemmay also transmit MPEG-2 images and dolby audio data.

Hereinafter, the conventional MPEG-2 image will be referred to as “maindata” or “normal data” for simplicity of the description. Herein, theenhanced data may be additionally processed with error correctionencoding as compared to the main data. Also, among the enhanced data, a½ enhanced data and a ¼ enhanced data refer to data being additionallyencoded at a ½ code rate and a ¼ code rate, respectively. Therefore,such enhanced data can perform excellent receptive functions over noisegenerated from channels and disturbance caused by multiple paths, ascompared to the main data. More specifically, the enhanced data that isencoded at a ¼ code rate (i.e., the ½ enhanced data) is more enhancedthan the enhanced data that is encoded at a ½ code rate (i.e., the ½enhanced data).

The general structure of the E8-VSB transmitting system will now bedescribed in detail with reference to FIG. 1. Referring to FIG. 1, amain and enhanced data multiplexing packet processor 111 multiplexes a ½enhanced data and a ¼ enhanced data to packet units and, then,multiplexes the multiplexed enhanced data and the main data into segmentunits, thereby outputting the multiplexed data to a first encoder 112.The first encoder 112 includes a randomizer 112a, a Reed-Solomon encoder112b, and a byte interleaver 112c, which are serially connected to anoutput terminal of the main and enhanced data multiplexing packetprocessor 111. The first encoder 112 having the above-describedstructure sequentially performs data randomizing, Reed-Solomon encoding,and data interleaving processes of the data packet, which is outputtedfrom the main and enhanced data multiplexing packet processor 111. Then,the first encoder 112 outputs the processed data packet to aconvolutional encoder 113.

The convolutional encoder 113 converts the byte data that is interleavedand outputted from the first encoder 112 into symbols. Then, theconvolutional encoder 113 convolutionally encodes enhanced data symbolsonly, which are then converted back to byte data and outputted to afirst decoder 114. The first decoder 114 includes a byte deinterleaver114a, a Reed-Solomon parity remover 114b, and a derandomizer 114c, whichare serially connected to an output terminal of the convolutionalencoder 113. The first decoder 114 having the above-described structureperforms data deinterleaving, Reed-Solomon parity removing, andderandomizing processes of the data packet being outputted from theconvolutional encoder 113. Then, the first decoder 114 outputs theprocessed data packet to an 8VSB transmitter 100.

The 8VSB transmitter 100, which has the same structure as the relatedart ATSC 8VSB transmitting system, includes an ATSC randomizer 101 (maybe omitted), an ATSC Reed-Solomon encoder 102, an ATSC byte interleaver103, a trellis encoder 104, a multiplexer 105, a pilot inserter 106, aVSB modulator 107, and an RF converter 108, More specifically, in the8VSB transmitter 100, as a set of data having the Reed-Solomon parityremoved passes through the Reed-Solomon encoder 102 and the ATSC byteinterleaver 103, the data is processed with Reed-Solomon encoding anddata interleaving processes. A 20-byte parity symbol is added to thedata during the Reed-Solomon encoding process, and an order of the datais switched (or changed) during the data interleaving process. Theinterleaved data is inputted to the trellis encoder 104. At this point,if the interleaved data is the enhanced data, a null bit of the enhanceddata is applied to a lower bit input terminal of the trellis encoder104, and information bit including information of the enhanced data isapplied to a higher bit input terminal of the trellis encoder 104.

The trellis encoder 104 pre-codes the data inputted to the higher bit,and the trellis encoder 104 encodes the data inputted to the lower bitand outputs the trellis-encoded data to the multiplexer 105. Themultiplexer 105 multiplexes a trellis-encoded symbol, a fieldsynchronization signal, a segment synchronization signal, and mapinformation, and the pilot inserter 106 inserts a pilot signal herein.Thereafter, the multiplexed signals and information and the pilot signalinserted therein are outputted to the VSB modulator 107. The VSBmodulator 107 modulates the signal having the pilot signal insertedtherein to an 8VSB signal having an intermediate frequency (IF), whichis then outputted to the RF converter 108. The RF converter 108 convertsthe VSB modulated signal to an RF frequency signal and transmits theconverted signal through an antenna.

The E8-VSB receiving system receiving the signal, which is E8-VSBmodulated and transmitted from the above-described E8-VSB transmittingsystem, will now be described in detail with reference to FIG. 2. Morespecifically, when the E8-VSB modulated RF signal is received through anantenna, a tuner 201 selects only a desired signal by a tuning process.Then, the tuner 201 converts the selected signal to an IF signal andoutputs the IF signal to an IF mixer 202. The IF mixer 202 down-convertsthe IF signal outputted from the tuner 201 to a baseband signal andoutputs the down-converted signal to a demodulator 203. Subsequently,the demodulator 203 demodulates the baseband signal to a VSB signal andoutputs the demodulated signal to an equalizer 204 and a map informationrecovery unit 205.

The map information recovery unit 205 recovers the transmitted E8-VSBmap information of a current field and outputs the recovered mapinformation to the equalizer 204 and an E8-VSB channeldecoder/demultiplexer 206. In addition, based on the E8-VSB mapinformation of the current field, the map information recovery unit 205generates a set of information indicating the attribute of each of thesymbols of the VSB signal. Then, the generated set of information isoutputted to the equalizer 204 and the E8-VSB channeldecoder/demultiplexer 206. More specifically, the map informationrecovery unit 205 determines whether the symbol is a main symbol (i.e.,a general E8-VSB signal, which may also be referred to as a normalsymbol) or an enhanced symbol. When the symbol is an enhanced symbol,the map information recovery unit 205 generates E8-VSB symbol attributeinformation notifying whether the enhanced symbol is ½ rate coded or ¼rate coded and, then, outputs the generated attribute information to theequalizer 204 and the E8-VSB channel decoder/demultiplexer 206.

The equalizer 204 receives the outputs from the E8-VSB channeldecoder/demultiplexer 206 and the map information recovery unit 205 andcompensates channel distortion included in the VSB-demodulated signal.Then, the equalizer 204 outputs the compensated signal to the E8-VSBchannel decoder/demultiplexer 206. More specifically, the equalizer 204may use the output of the map information recovery unit 205 to enhanceequalization, and the E8-VSB channel decoder/demultiplexer 206 mayperform a channel decoding process suitable to the currently receivedmode.

FIG. 3 illustrates a detailed block diagram of the E8-VSB channeldecoder/demultiplexer 206, wherein a separate data path for receivingenhanced data other than that for receiving the main data is included.In other words, by using the E8-VSB map information and the E8-VSBsymbol attribute information, which indicate multiplexing information ofan E8-VSB signal that is currently being received, the received signalis either decoded or separated to a corresponding mode. Thus, the E8-VSBreceiving system can receive a main VSB stream (MPEG TPS #1), and a ½enhanced stream (MPEG TPS #2) and a ¼ enhanced stream (MPEG TPS #3),which are both enhanced VSB streams. Herein, a “mode” refers to any oneof main data (i.e., the conventional ATSC 8VSB data), ¼ enhanced data,and ½ enhanced data.

Referring to FIG. 3, the E8-VSB channel decoder/demultiplexer 206, shownin FIG. 2, includes a main data decoder 300 and an enhanced data decoder310. Herein, the main data decoder 300 receives the equalized VSB symboland decodes the main data, and the enhanced data decoder 310 separatesand decodes the enhanced data and separates the decoded enhanced data tothe ½ enhanced data (MPEG TPS #2) and the ¼ enhanced data (MPEG TPS #3).The main data decoder 300 includes a Viterbi decoder/data deinterleaver301, an ATSC byte deinterleaver 302, an ATSC RS decoder 303, and an ATSCdata derandomizer 304.

More specifically, the main symbol equalized from the equalizer 204passes through the Viterbi decoder/12-way deinterleaver 301, the ATSCbyte deinterleaver 302, the ATSC RS decoder 303, and the ATSC dataderandomizer 304 of the main data decoder 300, thereby being decoded asthe main stream (MPEG TPS #1), which is similar to the conventional 8VSBchannel decoder. In other words, the main symbol is notified to be amain symbol by the EB-VSB data attribute generator. Therefore, the mainsymbol may be received through the path of the conventional channeldecoding mode. However, in case of the E8-VSB signal, since the maindata and the enhanced data are multiplexed, two types of modificationsare required to be made in the channel decoder. The Viterbi decodershould perform decoding that is suitable for each attribute, based onthe attributes of the VSB symbol. And, a separate data path for anenhanced VSB (EVSB) stream should be included.

The enhanced data decoder 310 is a data path for receiving and decodingthe EVSB stream, and the enhanced data decoder 310 includes an ATSC RSparity remover 311, an ATSC data derandomizer 312, a null bit remover313, an enhanced data deinterleaver 314, an enhanced RS decoder 315, anenhanced packet demultiplexer 316, a main and enhanced (M/E) multiplexer(MUX) packet processor 317, and two 164-to-188 packet converters (orfirst and second packet converters) 318 and 319. In the above-describedE8-VSB channel decoder/demultiplexer 206 of FIG. 3, the E8-VSB symbolthat is equalized from the equalizer 204 and the E8-VSB symbol attributeinformation that is created from the map information recovery unit 205are synchronized and inputted to the Viterbi decoder/12-waydeinterleaver 301.

The synchronized symbol that is inputted to the Viterbi decoder/12-waydeinterleaver 301 includes the main symbol and the enhanced symbol.Accordingly, the Viterbi decoder identifies the main symbol and theenhanced symbol in accordance with the E8-VSB symbol attributeinformation and performs a Viterbi decoding process accordingly. And, atthe same time, the Viterbi decoder also performs a 12-way deinterleavingprocess and outputs the corresponding result, in byte unit values, tothe ATSC byte deinterleaver 302. The value that is decided during thedecoding process in the Viterbi decoder is fed-back to the equalizer204. The ATSC byte deinterleaver 302 deinterleaves the byte-unit datathat is outputted from the Viterbi decoder/12-way deinterleaver 301.

More specifically, as a reverse process of the ATSC byte interleavershown in FIG. 1, the ATSC byte deinterleaver 302 deinterleaves theoutput of the Viterbi decoder/12-way deinterleaver 301 and, then,outputs the deinterleaved result in packet units. The packet data thatis outputted from the ATSC byte deinterleaver 302 is inputted to theATSC RS decoder 303 and the ATSC RS parity remover 311 of the enhanceddata decoder 310. The ATSC RS decoder 303 processes the output of theATSC byte deinterleaver 302 with RS decoding and outputs the RS decodedoutput to the ATSC data derandomizer 304. When the ATSC RS decoded datais derandomized from the ATSC data derandomizer 304, the derandomizeddata is finally outputted as a main signal (i.e., MPEG TPS #1). Sincethe enhanced streams are determined as null packets when observed fromthe conventional MPEG TP stream, thereby being ignored by the MPEGdecoder, only the MPEG TP stream of the main VSB is received withoutfailure.

The ATSC RS parity remover 311 of the enhanced data decoder 310 removesan ATSC RS parity portion from the packet data, which is outputted fromthe ATSC byte deinterleaver 302, and outputs the ATSC RS parity removeddata packet to the ATSC data derandomizer 312. The ATSC dataderandomizer 312 derandomizes the ATSC RS parity removed data packet,which is then outputted to the null bit remover 313. The null bitremover 313 removes all of the byte unit data, when the data is a maindata byte. When the data is a ½ enhanced data byte, the null bit remover313 removes the null bit, thereby outputting 2 bytes in 1 byte. And,finally, when the data is a ¼ enhanced data byte, the null bit remover313 removes the null bit, thereby outputting 4 bytes in 1 byte. Each ofthe byte are determined to be a main data byte, a ½ enhanced data byte,and a ¼ enhanced data byte in accordance with a set of E8-VSB byteattribute information outputted from the main and enhanced (M/E)multiplexer (MUX) packet processor 317.

The enhanced data deinterleaver 314 deinterleaves EVSB byte unit data,which are formed of significant bits outputted from the null bit remover313, and outputs the deinterleaved data to the enhanced RS decoder 315.The enhanced RS decoder 315 decodes the deinterleaved data and outputsthe decoded data to the enhanced packet demultiplexer 316. Subsequently,by using the E8-VSB map information and the field synchronization signaloutputted from the map information recovery unit 205, the enhancedpacket demultiplexer 316 separates the enhanced RS decoded data to a164-byte ½ enhanced data packet and ¼ enhanced data packet. The ½enhanced data packet is outputted to the first packet converter 318, andthe ¼ enhanced data packet is outputted to the second packet converter319. The first packet converter 318 separates and outputs the ½ enhanceddata packet, which is initially inputted as a 164-byte packet, into188-byte packet units without modifying the data (i.e., MPEG TPS #2).The second packet converter 319 outputs the ¼ enhanced data packet,which is initially inputted as a 164-byte packet, into 188-byte packetunits without modifying the data (i.e., MPEG TPS #3).

Among the enhanced channel decoder and demultiplexer of the E8-VSBreceiving system according to the present invention, the presentinvention is related to the embodiment of a Viterbi decoder that canperform decoding processes in accordance with the attribute of acorresponding E8-VSB symbol. Herein, instead of decoding theconvolutional encoder 113 and the trellis encoder 104 of the E8-VSBtransmitting system over two process steps, the E8-VSB receiving systemaccording to the present invention performs the decoding process in asingle step from the Viterbi decoder.

FIG. 11 illustrates a block diagram showing the structure of the Viterbidecoder according to a first embodiment of the present invention, whichis an example of an enhanced/main integrated Viterbi decoder. Referringto FIG. 11, the Viterbi decoder according to the first embodiment of thepresent invention includes a branch metric calculator 611, anaccumulate/compare/select (ACS) unit 612 of the positive decoder, anaccumulate/compare/select (ACS) unit 613 of the negative decoder, apolarity inversion estimator 614, a path history unit 615 of thepositive decoder, a path history unit 616 of the negative decoder, adecision selecting unit 617, a post decoder 618, and an outputmultiplexer (MUX) 619.

FIG. 15 illustrates a block diagram showing the structure of the Viterbidecoder according to a second embodiment of the present invention, whichis an example of an enhanced-only Viterbi decoder. Referring to FIG. 15,the Viterbi decoder according to the second embodiment of the presentinvention includes a branch metric calculator 811, anaccumulate/compare/select (ACS) unit 812 of the positive decoder, anaccumulate/compare/select (ACS) unit 813 of the negative decoder, apolarity inversion estimator 814, a path history unit 815 of thepositive decoder, a path history unit 816 of the negative decoder, adecision selecting unit 817, and an enhanced symbol re-ordering unit818. Prior to describing the difference between the Viterbi decoderaccording to the first embodiment of the present invention and theViterbi decoder according the second embodiment of the presentinvention, the convolutional encoder 113 and the trellis encoder of theE8-VSB transmitting system, shown in FIG. 1, and the co-relation betweenthe two member parts will now be described in detail.

FIG. 4A illustrates a detailed block diagram of the convolutionalencoder 113, which includes a 12-way symbol interleaver 401, an enhancedsymbol processor 402, and a 12-way symbol deinterleaver 403. Referringto FIG. 4A, the 12-way symbol interleaver 401 converts the data beinginputted in byte units to symbol units (i.e., units consisting of 2-bitnibbles X2 and X1). Then, the 12-way symbol interleaver 401 interleavesthe converted data, which are outputted to the enhanced symbol processor402. When the inputted data is a main symbol, the inputted data bypassesthe enhanced symbol processor 402 and proceeds to the 12-way symboldeinterleaver 403. Meanwhile, when the inputted data is an enhancedsymbol, symbol processing is performed only on the data (X2) that isinputted as the higher bit, and the symbol processed data is outputtedto the 12-way symbol deinterleaver 403, whereas the data (X1) inputtedas the lower bit is discarded. Subsequently, the 12-way symboldeinterleaver 403 deinterleaves the data being outputted from theenhanced symbol processor 402, outputs the deinterleaved data symbolsinto byte units, and outputs to the first decoder 114.

FIG. 4B illustrates a detailed block diagram of the enhanced symbolprocessor 402. Herein, an adder 411 adds the data (X2) that is inputtedas the higher bit and the data that is fed-back from a register 414.Then, the adder 411 outputs the added data to a multiplexer 412. Whenthe symbol being inputted is a main symbol, the multiplexer 412 selectsthe output of the adder 411. And, when the symbol being inputted is anenhanced symbol, the adder 411 selects the data (X2) that is inputted asthe higher bit. Then, the multiplexer 412 outputs the selected data tothe registers 413 and 414 and an adder 415. The register 413 delays theoutput of the multiplexer 412 by one symbol and outputs the delayedoutput to the adder 415. The adder 415 adds the output of themultiplexer 412 and the output of the register 413 and, then, outputsthe added output as the higher bit (X2′). Herein, the register 413 is atype of delayer, and such function also applies equally to otherregisters. The register 414 delays the output of the multiplexer 412 byone symbol and feeds-back the delayed output to the adder 411.

Subsequently, when the symbol being inputted is a main symbol, themultiplexer 416 selects the output of the register 417. And, when thesymbol being inputted is an enhanced symbol, the multiplexer 416 selectsthe output of the register 420. Then, the multiplexer 416 outputs theselected output to the register 417. The register 417 delays the outputof the multiplexer 416 by one symbol unit and, then, outputs the delayedoutput to the adder 418 and simultaneously feeds-back the delayed outputto the multiplexer 416. The adder 418 adds the data (X2) being inputtedas the higher bit and the output of the register 417 and, then, outputsthe added data to the multiplexer 419.

When the symbol being inputted is a main symbol, the multiplexer 419selects the output of the register 420. And, when the symbol beinginputted is an enhanced symbol, the multiplexer selects the output ofthe adder 418. Thereafter, the multiplexer 419 outputs the selectedoutput to the register 420. The register 420 delays the output of themultiplexer 419 by one symbol unit and, then outputs the delayed outputto another multiplexer 421 and, simultaneously, feeds-back the delayedoutput to the multiplexers 417 and 419. When the inputted signal is amain symbol, the multiplexer 421 selects the data (X1) being inputted asthe lower bit and outputs the selected data as a lower bit (X1′). Whenthe inputted signal is an enhanced symbol, the multiplexer 421 selectsthe output of the register 420 and outputs the selected output as alower bit (X1′).

A total of 12 enhanced symbol processors 402 having the above-describedstructure are included in the E8-VSB convolutional encoder 113. Thesymbol processing of the enhanced symbol processor 402 may varydepending upon whether the symbol that is being inputted is a mainsymbol or an enhanced symbol. More specifically, referring to FIG. 4B,the select signal (i.e., M/E flag) that is inputted to the multiplexer412, 416, 419, and 421 indicates whether the symbol (i.e., symbolconsisting of 2-bit nibbles X1 and X2) currently being inputted is amain symbol or an enhanced symbol, which can be encoded at a ½ code rateor a ¼ code rate.

FIG. 4C illustrates a data path indicated from the enhanced symbolprocessor, when the inputted symbol is a main symbol. More specifically,when the symbol that is inputted is a main symbol, the data (X1) beinginputted as a lower bit is bypassed as X1′ through the multiplexer 421,and the data (X2) being inputted as a higher bit is bypassed as X2′through the adder 411, the multiplexer 412, the registers 413 and 414,and the adder 415. The adder 411 and the register 414 have the structureof a pre-coder, and the adder 415 and the register 413 have thestructure of a post-decoder. Herein, since the functions of thepre-coder and the post-decoder are canceled out with respect to eachother, the data (X2) being inputted as the higher bit may be directlybypassed as X2′.

FIG. 4D illustrates a data path indicated from the enhanced symbolprocessor, when the inputted symbol is an enhanced symbol. Morespecifically, when the symbol being inputted is an enhanced symbol, thedata (X2) being inputted as the higher bit is post-decoded from thepost-decoder, which consists of the register 413 and the adder 415, andthen outputted as X2′. Also, the data (X2) being inputted as the higherbit is convolutionally encoded from the convolution encoder, whichconsists of the register 417, the adder 418, and the register 420. And,the parity bit that is generated during the encoding process isoutputted as X1′, and the data (X1) that is inputted as the lower bit isdiscarded.

FIG. 5 illustrates an example of concatenation between the enhancedsymbol processor and the trellis encoder. In the E8-VSB transmittingsystem, a plurality of blocks actually exists between the enhancedsymbol processor and the trellis encoder. However, the Viterbi decoder301 in the enhanced channel decoder/demultiplexer 206 decodes theequalized symbol in a manner that the enhanced symbol processor and thetrellis encoder by assuming they are directly concatenated. Referring toFIG. 5, the trellis encoder 104 includes a pre-coder 510 connected tothe higher bit, and the convolution encoder 520 connected to the lowerbit. Herein, the trellis encoder 104 encodes the two input bits X2 andX1, which are outputted as three output bits C2, C1, and C0. Morespecifically, the data (X2) inputted as the higher bit is pre-coded fromthe pre-coder 510, thereby creating an output bit (C2). Also, the data(X1) being inputted as the lower bit is directly bypassed and outputtedas output bit (C1). Simultaneously, the data (X1) being inputted as thelower bit is encoded from the convolution encoder 520. The parity bitcreated during this process becomes the output bit (C0). In other words,the output bit (C0) is decided in accordance with a value stored in theregister (M0).

FIG. 5A illustrates the enhanced symbol processor and a trellis encoderbeing concatenated, when the inputted symbol is a main symbol. As shownin FIG. 7C, when the inputted symbol is a main symbol, the two inputtedbits X2 and X1 are directly bypassed as X2′ and X1′ and inputted to thetrellis encoder 104. More specifically, the higher bit (X2) that isinputted to the enhanced symbol processor 402 is inputted directly tothe pre-coder 510 of the trellis encoder 104. In addition, the lower bit(X1) that is inputted to the enhanced symbol processor 402 is inputteddirectly to the convolution encoder 520 of the trellis encoder 104.

FIG. 5B illustrates the enhanced symbol processor and a trellis encoderbeing concatenated, when the inputted symbol is an enhanced symbol. Asshown in FIG. 4D, the data (X1) being inputted as the lower bit isdiscarded, and the data (X2) being inputted as the higher bit passesthrough the post-decoder and is outputted to the trellis encoder 104 asX2′. In addition, the data (X2) that is inputted as the higher bit isconvolutionally encoded from the convolution encoder, and the parity bitthat is generated during the process is outputted to the trellis encoder104 as X1′. In other words, the higher bit (X2′), which is post-decodedand outputted from the enhanced symbol processor 402, is inputted to thepre-coder 510 of the trellis encoder 104. On the other hand, the lowerbit (X1′), which is convolutionally encoded and outputted from theenhanced symbol processor 402, is inputted to the convolution encoder520 of the trellis encoder 104. Since the functions of the post-decoderof the enhanced symbol processor 402 and the pre-coder of the trellisencoder 104, which are applied to the X2 of the enhanced symbol, may becanceled out, X2 is directly bypassed as C2, as shown in FIG. 5C.Therefore, the Viterbi decoder of the E8-VSB receiving system accordingto the present invention may perform decoding processes of the mainsymbol and the enhanced symbol by using Viterbi decoding algorithms thatare generally used in the examples shown in FIG. 5A and FIG. 5C,respectively.

FIG. 6 illustrates a state transition diagram of the enhanced symbol andthe main symbol. More specifically, when the symbol is an enhancedsymbol, the states for the registers M3, M2, M1, M0 (shown in FIG. 5C)are defined herein, and 16 different states exist in total. When thesymbol is a main symbol, M3 and M2 maintain the values changed from theprevious enhanced symbol, and so the state transition pattern may berepeated 4 times, as shown in FIG. 6. In other words, when the symbol isa main symbol, as shown in FIG. 5A, the input data X2 and X1 is bypasseddirectly from the enhanced symbol processor 402 to the trellis encoder104.

Referring to FIG. 6, when the symbol is an enhanced symbol, the inputbit X2 changes the state. And, conversely, when the symbol is a mainsymbol, the input bit X1 changes the state. More specifically, this isbecause the input bit X1 is discarded and the input bit X2 passesthrough 4 registers M3, M2, M1, and M0, as shown in FIG. 5C, when thesymbol in the enhanced symbol. On the other hand, when the symbol is themain symbol, the input bit X1 passes through the registers M1 and M0, asshown in FIG. 5A. At this point, the enhanced symbol is identified asone of a ½ enhanced symbol and a ¼ enhanced symbol.

However, the enhanced symbol processor (shown in FIG. 4B) treat theinput symbol equally, when the symbol is the enhanced symbol, withoutdetermining whether the input symbol is the ½ enhanced symbol or the ¼enhanced symbol. Unlike the ½ enhanced symbol, in a byte expanderincluded in the E8-VSB transmitting system, the input bit is repeated 2times, when the symbol is a ¼ enhanced symbol. However, the repeated ¼enhanced symbol may be randomly changed by a data randomizer, therebycausing the repeated symbols to be identical to or different from oneanother. And, since the E8-VSB receiving system is aware of theoperations of the data randomizer, the E8-VSB receiving system iscapable of identifying whether the repeated symbols are identical to ordifferent from one another.

FIG. 7A illustrates a state transition diagram of a ¼ enhanced symbol,when repeated ¼ symbols are identical to one another. And, FIG. 7Billustrates a state transition diagram of a ¼ enhanced symbol, whenrepeated ¼ symbols are different from one another. In case of the ¼enhanced symbol, the Viterbi decoding process should be performed in 2symbol units, so as to obtain additional coding gain from the Viterbidecoder. Referring to FIG. 7A, when the repeated ¼ enhanced symbols areidentical to one another even after passing through the data randomizer,the Viterbi decoding process is performed while only taking intoconsideration the path having identical data values during 2 symbols.For example, when the state is ‘0000’, only the path having both data X2values that are identically equal to ‘1’ and ‘0’ is accounted for, andthe paths having different X2 values are excluded from the decodingprocess, thereby enhancing decoding reliability.

Conversely, referring to FIG. 7B, when the ½ enhanced symbols that arerepeated from the null bit expander are different from one another afterpassing through the data randomizer, the Viterbi decoding process isperformed while only taking into consideration the paths havingdifferent data values during 2 symbols. For example, when the state is‘0000’, only the paths having data X2 values different from one another(i.e., ‘0’→‘1’ and/or ‘1’→‘0’) are accounted for, and the remainingpaths are excluded from the decoding process.

In the E8-VSB transmitting system including the enhanced mode, tomaintain compatibility with the conventional ATSC 8VSB receiver, theoutput of the E8-VSB convolution encoder 113 is not directly inputted tothe trellis encoder 104 but inputted to the trellis encoder 104 througha series of process steps. Such process steps include passing througheach of the ATSC data byte deinterleaver 114a, the RS parity byteremover 114b, the ATSC RS encoder 102, and the ATSC data byteinterleaver 103.

Further, in the enhanced symbol processor 402, the main symbol isbypassed, and only the enhanced symbol is processed with additionalencoding. However, the parity byte calculated from the ATSC RS encoder112b, prior to such additional encoding process, does not fit themodified (or changed) data packet. And, accordingly, when the RSdecoding process is performed, the conventional ATSC 8VSB receiverdetermines that an error has occurred in the enhanced data packet.Therefore, in order to maintain the compatibility with the conventionalATSC 8VSB receiver, the output of the E8-VSB convolution encoder 113 isATSC RS encoded from the ATSC RS encoder 102, so as to recalculate theparity byte. The above-described series of process steps are used torecalculate the parity byte. However, when the recalculated parity byte,which is converted to a symbol, is inputted to the trellis encoder 104so as to be encoded from the pre-coder, the polarity of the symbol maybe inversed, instead of the enhanced symbol being bypassed.

FIG. 8 illustrates an example of a polarity inversion in the enhancedsymbol. Referring to FIG. 8, the term “compatibility processing” refersto the above-described series of process steps that are used formaintaining compatibility. As shown in FIG. 8, P represents the MSBamong the 2 bits when the ATSC RS parity byte, which is added to theenhanced data packet, is converted to a symbol, E represents the MSB ofan enhanced symbol, and M represents the MSB of a main symbol.Furthermore, P′ represents an MSB of an ATSC RS parity symbol that isrecalculated after passing through the compatibility processing. Inother words, P is recalculated as P′ from the compatibility processing.

Referring to FIG. 8, the adder 411, the multiplexer 412, the registers413 and 414, and the adder 415 of the enhanced symbol processor 402,shown in FIG. 4B, are collectively referred to as a pre-coder bypass forsimplicity of the description. At this point, it is assumed that data isinputted to the pre-coder bypass of the enhanced symbol processor 402 bythe order of P, M, and E. Additionally, as shown in FIG. 8, the initialvalues of registers R2, R1, and R0 are all equal to ‘0’, and the Psymbol is assumed and processed as the main symbol at the enhancedsymbol processor 402. In this case, the output (X2′) of the pre-coderbypass of the enhanced symbol processor 402 is generated in the order ofP, M, and P+M+E. These outputs pass through the compatibility processingand are inputted to the pre-coder 510 of the trellis encoder 104.Therefore, the output (C2) of the pre-coder 510 of the trellis encoder104 is generated in the order of P′, P′+M, and P′+P+E.

In conclusion, instead of being directly bypassed as itself, theenhanced symbol is outputted as P′+P+E. At this point, when P′ and P areequal to one another (i.e., P′=P), P′+P+E=E, thereby bypassing E asitself. However, when P′ and P are different from one another (i.e.,P′≠P), the value E is inversed and outputted. Among the 3-bit output ofthe trellis encoder 104, when C2 being the MSB is inversed, the mappingof the 8-level VSB signal is configured as follows:−7<=>+1, −5<=>+3, −<=>+5, −1 <=>+7.

More specifically, the VSB modulator 107 maps the 3 output bits (C2, C1,and C0) outputted from the trellis encoder 104 as the corresponding8-level modulation value, and then the VSB modulator 107 outputs themapped value. For example, when the value of C2C1C0 is ‘000’, the mappedvalue is ‘−7’, when the value of C2C1C0 is ‘011’, the mapped value is‘−1’, and when the value of C2C1C0 is ‘100’, the mapped value is ‘+1’.Accordingly, when the value of C2C1C0, which is normally supposed to be‘000’, becomes ‘100’ due to an inversion in the C2 value, the mappedvalue becomes ‘₊1’ instead of ‘−7’. Therefore, when the symbol is anenhanced symbol, the Viterbi decoder of the E8-VSB receiving systemshould assume whether the polarity of the output C2 bit, which isoutputted from the trellis encoder of the transmitter, has beeninversed. In the present invention, such process will be referred to asa polarity inversion of an enhanced symbol.

A “Viterbi algorithm” is an algorithm that calculates the probability ofa state transition path according to the time of the trellis encoder andselects the path having the highest probability. A “branch metric” is acalculated value of the probability for each branch with respect to thestate transition of the current time, and a “path metric” refers to anaccumulation of the branch metric, which is obtained in accordance withthe corresponding time. The branch metric can be obtained by calculatinga Euclidean distance between the output level of each branch and theinput signal of the Viterbi decoder. At this point, since each of theenhanced symbol and the main symbol received at the E8-VSB receivingsystem is an 8-level signal, the branch metric calculator calculates theEuclidean distance of the input signal for each of the 8 standard levelsby using Equation 1 below, so as to obtain 8 different metric valuesBM(b):

Equation 1BM(b)=(r_(n)−L_(b))², wherein L_(b)=(2b−7) and 0≦b≦7,

wherein r_(n) represents the signal inputted to the Viterbi decoder attime n, and L_(b) corresponds to a reference 8-level VSB signal.

The path metric is a probability value of a transition process of astate, more specifically, a path, and which is an accumulated value ofthe branch metric. The accumulate/compare/select (ACS) unit of theViterbi decoder calculates the value for each path metric and comparesthe calculated values, thereby selecting the path that has the lowestpath metric value (i.e., the metric value having the highestprobability). More specifically, the ACS unit adds the branch metric,which corresponds to 2 branches for each state, with the path metric ofa previous state, which is connected to the corresponding branch, andthen selects and stores the smaller value of the two calculated values.FIG. 9 illustrates an example of a path metric calculation process ofthe enhanced symbol and the main symbol. Referring to FIG. 9, theprocess of calculating the path metric is described by using state 0000for each of the enhanced symbol and the main symbol.

When the input symbol is the enhanced symbol, as shown in part (a) ofFIG. 9, the previous state (i.e., state of ‘t−1’) that can be merged asthe state 0000 of ‘t’ are state 0000 and state 1000. During state 0000of ‘t−1’, when ‘0’ is inputted as the input X2 of the enhanced symbolprocessor 402, the reference 8-level value that is outputted from thetrellis encoder 104 becomes ‘−7’, if there is no polarity inversion, andbecomes ‘+1’, if polarity inversion occurs, thereby creating a path forthe state 0000 of ‘t−1’ to be transited to state 0000 of ‘t’. Meanwhile,during state 1000 of ‘t−1’, when ‘1’ is inputted as the input X2, thereference 8-level value becomes ‘+1’, if there is no polarity inversion,and becomes if polarity inversion occurs, thereby creating a path forthe 1000 state of ‘t−1’ to be transited to state 0000 of ‘t’.

More specifically, if polarity inversion does not occur, the branchmetric value of the transition path from state 0000 of ‘t−1’ to state0000 of ‘t’ is equal to (inputted signal-(−7))². Conversely, if thepolarity inversion occurs, the branch metric value of the transitionpath from state 0000 of ‘t−1’ to state 0000 of ‘t’ is equal to (inputtedsignal-(+1))². Thereafter, at state 0000 of ‘t’, the newly calculatedbranch metric value is added to the previously accumulated path metricvalue. Simultaneously, in another path that can be merged as state 0000of ‘t’ (i.e., the transition path from state 1000 of ‘t−1’ to state 0000of ‘t’), the branch metric value is added to the previously accumulatedpath metric value. Further, the added results of the two states that aremerged as state 0000 of ‘t’ are compared, and the path having the lowestadded value is selected as the surviving (or remaining) path.

The method for calculating the path metric value of state 0000 of ‘t’will now be described in detail. Firstly, for each of the two branchesthat are merged as state 0000 of ‘t’, the branch metric value is addedto the path metric value of ‘t−1’, thereby obtaining the current pathmetric values. Secondly, the two current path metric values arecompared, so as to select the path having the lowest path metric value,as the surviving (or remaining) path. Thereafter, the path metric valueis renewed (or updated) with the path metric value of the selected pathfor a following ACS calculation. Finally, a survivor of the selectedpath and a set of path selecting information are outputted to the pathhistory unit. Herein, the survivor becomes the input X2 bit of theenhanced symbol processor 402. Furthermore, C2 bit is additionallyincluded herein for the enhanced/main integrated Viterbi decoder, whichwill be described in detail in a later process with reference to FIG.11, and outputted to the path history unit.

When the input symbol is the main symbol, as shown in part (b) of FIG.9, the previous states (i.e., states of ‘t−1’) that can become the state0000 of ‘t’ include state 0000 and state 0010. At state 0000 of ‘t−1’,when ‘0’ is inputted as the input X1 of the enhanced symbol processor402, the level value that is outputted from the trellis encoder 104becomes ‘−7’ or ‘+1’, depending upon the input X2 of the trellis encoder104, thereby forming the state 0000 path of ‘t’. Meanwhile, during state0010 of ‘t−1’, when ‘1’ is inputted as the input X1, the level valuebecomes ‘−3’ or ‘+5’, depending upon the input X2, thereby forming thestate 0000 path of ‘t’.

Accordingly, the method for calculating the path metric value of state0000 of ‘t’ will now be described in detail. First of all, in each path(i.e., branch) of state 0000, two output level values may be obtaineddepending upon the input X2. Therefore, the two branch metric values arecompared, and the lower one of the two values is selected. Then, the C2bit corresponding to the selected level value is outputted. Secondly,for each of the two branches that are merged as state 0000 of ‘t’, thebranch metric value selected from the above-described first step, isadded to the accumulated path metric value of ‘t−1’, thereby obtainingthe current path metric values.

Thirdly, the two current path metric values that are calculated in thesecond step are compared, and the lower one of the two values isselected as the surviving (or remaining) path. Thereafter, the pathmetric value is renewed (or updated) with the path metric value of theselected path for a following ACS operation. And, finally, a survivor ofthe selected path and a set of path selecting information are outputtedto the path history unit. The survivor includes X1 of the selected pathand C2 bit of the first step. Herein, the C2 bit is one of the MSB amongthe output of the trellis encoder 104, which is decoded as the X2 bitafter being processed with post-decoding. More specifically, in case ofthe main symbol, the survivor for each state is C2 and X1. An example ofcalculating an accumulated path metric of state 0000 and renewing (orupdating) the calculated metric path is shown in part (b) of FIG. 9. Theaccumulated path metric of other states are also calculated and renewed(or updated) in accordance with the state transition diagram of eachinputted symbol.

Since the state for each of the enhanced symbol and the main symbol istransited differently, the ACS unit requires an E/M flag that canidentify the enhanced symbol and the main symbol. In addition, an H/Qflag that can identify whether the enhanced symbol is a ½ enhancedsymbol or a ¼ enhanced symbol is also required. When the input symbol isthe ¼ enhanced symbol, the ACS units require a PNEQ flag that indicateswhether the repeated bits, which are repeated from the null byteexpander, are identical to or different from one another after passingthrough the ATSC data randomizer. Meanwhile, in order to estimate theabove-described polarity inversion of the enhanced symbol, the ACS unitsalso requires a FLIP signal that indicates at which point the ATSC RSparity symbol is added to the enhanced data segment.

The above-described 4 control signals, more specifically, the E/M flag,the H/Q flag, the PNEQ flag, and the FLIP signal are E8-VSB symbolattribute information that is outputted from the map informationrecovery unit, which is included in the E8-VSB receiving system. Inconclusion, the inputs that are required by the ACS unit includes theE/M flag, the H/Q flag, the PNEQ flag, the FLIP signal, and the branchmetric values for 8 reference levels. In addition, a control signalindicating the sections for the field synchronization signal and thesegment synchronization signal, which is identical to that of theViterbi decoder of the conventional ATSC 8T-VSB receiver, is alsorequired. Hereinafter, the description of the control signal indicatingthe field synchronization signal and the segment synchronization signalwill be omitted. The E8-VSB transmitting system includes 12 enhancedsymbol processors and 12 trellis encoders. And, accordingly, the E8-VSBreceiving system includes 12 Viterbi decoders, which correspond to theenhanced symbol processors and the trellis encoders of the E8-VSBtransmitting system.

FIG. 10 illustrates an example of a set of control signals beinginputted to any one of the 12 Viterbi decoders. Referring to FIG. 10, Mrepresents the main signal, represents the ½ (half) enhanced symbol, andQ represents the ¼ (quarter) enhanced symbol. Furthermore, P representsa symbol being a conversion of the ATSC RS parity byte that is added tothe enhanced data packet. When the E/M flag is high, the current inputsymbol is an enhanced symbol, and when the E/M flag is low, the currentinput symbol is a main symbol.

The H/Q signal is only valid in the enhanced symbol section. In thiscase, when the H/Q signal is low, the enhanced symbol is the ½ enhancedsymbol, and when the H/Q signal is high, the enhanced symbol is the ¼enhanced symbol. Herein, the PNEQ signal is only valid in the ¼ enhancedsymbol section, the level of which changes to 2 symbol units. When thelevel of the PNEQ signal is low, the repeated ¼ enhanced data arechanged to different values at the ATSC randomizer. Conversely, when thelevel of the PNEQ signal is high, the repeated ¼ enhanced data arechanged to identical values at the ATSC randomizer. The FLIP signalindicates the point where the polarity conversion of the enhanced symboloccurs. Herein, the FLIP signal is high during the section of the ATSCRS parity symbol that is added to the enhanced data packet.

Meanwhile, when performing an ACS operation of the ¼ enhanced symbol,the basic principle is identical to that of the ½ enhanced symbol.However, the operation of the ACS unit varies according to each symbol.More specifically, when the E/M flag is high and when the H/Q flag ishigh, the input symbol is the ¼ enhanced symbol. In this case, each ofthe two symbols performs an ACS operation depending upon the PNEQsignal. The decoding process based on the PNEQ signal is described abovein detail with reference to FIG. 6 to FIG. 7B.

In the ACS unit, which is similar to the conventional ATSC 8T-VSBViterbi decoder, a hardware for performing accumulating, comparing, andselecting operations shares 12 Viterbi decoders, wherein only theembodiment of the path metric for each Viterbi decoder is necessary. Thehardware sharing is enabled because the 12 Viterbi decoders are operatedsequentially (i.e., in turns) and not simultaneously. Each of theViterbi decoders consists of a positive decoder and a negative decoder.Since each of the positive decoder and the negative decoder is formed of12 different states, the total number of path metrics required herein isequal to (12×2×16=384).

As described above, since a polarity inversion may occur when the inputsymbol is the enhanced symbol, the occurrence of the polarity inversionneeds to be estimated. In order to estimate such polarity inversion, acomparison should be made between a path metric value of a decodingprocess, which is performed under the assumption that polarity inversiondid not occur, and a path metric value of another decoding process,which is performed under the assumption that polarity inversionoccurred. After comparing the two path metric values, the lower one ofthe two values (i.e., the value having the higher probability) isselected. Then, the estimation is made in accordance with the selectedresult. Therefore, in order to estimate such polarity inversion of theenhanced symbol, 2 decoders are required. Hereinafter, one of thedecoders is referred to as a “positive decoder”, provided that polarityinversion did not occur, and the other one of the decoders is referredto as a “negative decoder”, provided that the polarity inversionoccurred.

The process of estimating the polarity inversion of the enhanced symbolwill now be described. First of all, a minimum path metric value foreach of the positive and negative decoders of the ACS unit iscalculated. Herein, the minimum path metric value refers to the lowestvalue among the calculated minimum values for each state at ‘t’.Secondly, the minimum path metric values of the positive decoder and thenegative decoder are compared, and the lower one of the two values isoutputted as the polarity signal of the decoder. For example, when theminimum path metric value of the positive decoder is lower than theminimum path metric value of the negative decoder, the polarity signalis positive (+). In other words, the signal selects the positivedecoder.

And, finally, in the section where the FLIP signal is low, the pathmetric values for each state of the decoders that are not selected bythe polarity signal are overwritten by the path metric valuescorresponding to the selected decoders, and then the ACS operation isperformed. For example, provided that the positive decoder is theselected decoder, the path metric values for each state of the positivedecoder written over the path metric values for each state correspondingto the negative decoder. At this point, if the positive decoder isselected, then it is assumed that the polarity inversion did not occur.Conversely, if the negative decoder is selected, then it is assumed thatthe polarity inversion has occurred. Furthermore, the polarity inversionestimator, which estimates the polarity inversion as described above,may also be shared among the 12 Viterbi decoders.

In the Viterbi algorithm, the input of a surviving (or remaining) path,i.e., the survivor, which is selected from each state during the ACSoperation, is stored, so as to maintain the path history during the timelength of a decoding depth. The path history unit receives polaritysignals (i.e., signals selecting one of the positive decoder and thenegative decoder) outputted from the polarity inversion estimator andstate numbers having minimum path metrics outputted from the ACS unit.Then, the path history unit traces-back the path history of thecorresponding state, so as to output the final decision. In the pathhistory unit, in the section where the FLIP signal is low, the pathhistory for each state of the decoders that are not selected by thepolarity signal are overwritten by the path history of the selecteddecoders, thereby renewing (or updating) the path history.

According to a general Viterbi decoding process, the symbols inputted tothe Viterbi decoder includes the enhanced symbol and the main symbol.Therefore, the enhanced symbol survivor and the main symbol survivor arestored in the path history unit in the same order. Thus, the Viterbidecoder becomes the enhanced/main (E/M) integrated decoder, whichdecodes both the enhanced symbol and the main symbol. Also, the finaloutputs of the decoder are outputted in the same order at regular timeintervals with the corresponding inputs. In the present invention, theE8-VSB Viterbi decoder includes 16 states, each state outputting 2survivor bits from the ACS unit, which are then stored according to thetime length of the decoding depth. Therefore, the E8-VSB Viterbi decoderrequires a memory having the capacity of 16× decoding depth×2 bits.Furthermore, since the history for each of the positive decoder and thenegative decoder should be maintained individually, the memory shouldhave the capacity of 2×16× decoding depth×2 bits. Meanwhile, since 12Viterbi decoders are required in the present invention, the memory ofthe E8-VSB Viterbi decoder requires a total capacity of 12×2×16×decoding depth×2 bits.

FIG. 11 illustrates an enhanced/main integrated Viterbi decoderaccording to a first embodiment of the present invention. The branchmetric calculator 611 calculates the Euclidian distance between theinput symbol and each of the 8 reference output levels, so as to obtaina total of 8 branch metric values. Then, the branch metric calculator611 outputs the calculated branch metric values to the ACS unit 612 ofthe positive decoder and the ACS unit 613 of the negative decoder. Atthis point, the 8-level reference values used for calculating the branchmetric value with the input symbol are −7, −5, −3, −1, +1, +3, +5, and+7. Particularly, −7, −5, −3, and −1 are reference output level valueswhen C2 bit is equal to ‘0’, and +1, +3, +5, and +7 are reference outputlevel values when C2 bit is equal to ‘1’.

In addition, as described above, the polarity inversion may occur whenthe input symbol is the enhanced symbol. More specifically, at state0000 of ‘t−1’, when ‘0’ is inputted as the input X2 of the enhancedsymbol processor 402, the reference 8-level value that is outputted fromthe trellis encoder 104 becomes-7, if the polarity inversion does notoccur, and become +1, if the polarity inversion occurs, thereby forminga transition path from state 0000 of ‘t−1’ to state 0000of ‘t’.Therefore, the metric value becomes different depending upon whetherpolarity inversion occurs or not within the same path.

Accordingly, the ACS unit 612 of the positive decoder receives thebranch metric value of the instance when the polarity inversion has notoccurred from the branch metric calculator 611. Then, the ACS unit 612of the positive decoder receives the control signals, such as the E/Msignal, the H/Q signal, the FLIP signal, and the PNEQ signal, from themap information recovery unit, so as to perform the ACS operation. Inother words, for each two branches of each state, each of the ACS unit612 of the positive decoder and the ACS unit 613 of the negative decoderrespectively adds the corresponding branch metric value and the pathmetric value of a previous state, which is connected to thecorresponding branch. Then, each of the ACS units 612 and 613 selectsand stores the smallest value that is obtained. Thus, the survivor andthe path selecting information are outputted to the path history units615 and 616 of the positive decoder and the negative decoder,respectively. For example, when the inputted symbol is the enhancedsymbol, the survivor for each state becomes the X2 and C2 bits, and whenthe inputted symbol is the main symbol, the survivor for each statebecomes the X1 and C1 bits.

In addition, among the path metric values for each state, each of theACS unit 612 of the positive decoder and the ACS unit 613 of thenegative decoder selects the lowest value as the path metric value andoutputs the selected value to the polarity inversion estimator 614.Then, the state number having the minimum (or lowest) path metric valueis outputted to the path history unit 615 of the positive decoder andthe path history unit 616 of the negative decoder.

In the present invention, in the symbol section (i.e., the section wherethe FLIP signal is high) causing the polarity inversion, the path metricvalue for each state of the selected decoder, which is selected inaccordance with the polarity estimated from the polarity inversionestimator 614, is written over the path metric value for each state ofthe non-selected decoder. Thereafter, the ACS operation is performed.The polarity inversion estimator 614 receives the FLIP signal and theminimum path metric value from the ACS unit 612 of the positive decoderand the ACS unit 613 of the negative decoder and estimates the polarityinversion. For example, if it is determined that the minimum path metricvalue outputted from the ACS unit 613 of the negative decoder is smaller(or lower) than the minimum path metric value outputted from the ACSunit 612 of the positive decoder, then the polarity inversion estimator614 estimates that polarity inversion has occurred. Conversely, if it isdetermined that the minimum path metric value outputted from the ACSunit 613 of the negative decoder is greater than the minimum path metricvalue outputted from the ACS unit 612 of the positive decoder, then thepolarity estimator 614 estimates that polarity inversion has notoccurred. Subsequently, the polarity estimator 614 outputs the polarityresult to each of the ACS unit 612 and the path history unit 615 of thepositive decoder and the ACS unit 613 and the path history unit 616 ofthe negative decoder, respectively.

Each of the path history unit 615 of the positive decoder and the pathhistory unit 616 of the negative decoder receives the control signals,such as the E/M signal, the H/Q signal, the FLIP signal, and the PNEQsignal, the survivor, path selecting information, and the state numberwhich has a minimum path metric value among states, so as to maintainthe path history during the decoding depth. In addition, the statecorresponding to the minimum path metric value for each of the decodersis back-traced, so that the survivor of a previous time, which precedesthe time length of the decoding depth, is outputted to the decisionselecting unit 617 as the decoding decision value. Furthermore, in thesection where the FLIP signal is high, each of the path history units615 and 616 of the positive decoder and the negative decoder writes thepath history of the selected decoder, which is selected in accordancewith the polarity signal, over the path history of the non-selecteddecoder.

The decision selecting unit 617 selects the decoding decision value ofthe selected decoder, which is selected in accordance with the polaritysignal of the polarity inversion estimator 614, and outputs the selectedvalue to the post-decoder 618 and the output multiplexer 619. Forexample, when the positive decoder is selected by the polarity inversionestimator 614, the decoding decision value outputted from the pathhistory unit 615 of the positive decoder is selected and outputted.Among the decoding decision values, the C2 bit is outputted to thepost-decoder 618, and the X2 or X1 bit is outputted to the outputmultiplexer 619.

More specifically, since the main symbol is pre-coded at thetransmitting terminals, a post-decoding process (i.e., the reverseprocess of pre-coding) should be performed. In this case, thepost-decoder 618 post-decodes the C2 bit without identifying whether thesymbol is a main symbol or an enhanced symbol and, then, outputs thepost-decoded C2 bit to the output multiplexer 619. When the symbol isthe enhanced symbol, the output multiplexer 619 outputs the X2 bitinstead of the post-decoded result, as the higher bit, and outputs adummy bit as the X1 bit, which is the lower bit. On the other hand, whenthe symbol is the main symbol, the X1 bit is outputted as the lower bitand the post-decoded result is outputted as the higher bit.

Since the enhanced symbol is processed with additional convolutionencoding, as compared with the main symbol, there is a significantdifference between the enhanced symbol and the main symbol inperformance after being decoded. However, when the enhanced symbol andthe main symbol are inputted to the path history unit in combination,due to the small number of enhanced symbols within a set portion of thedecoding depth, the valid decoding depth of the enhanced symbols may bereduced. As a result, the main symbols may cause the decoding effect ofthe enhanced symbols to be deficient. Such problems may worsen as theamount of the enhanced data becomes lower. Therefore, in order to reducethe influence of the main symbol on the enhanced symbol, only theenhanced symbols should be inputted to the path history unit, so as toensure a set portion of valid decoding depth. Since the decision of theenhanced symbol is performed only on the X2 bit, the memory capacityrequired in the path history unit is 12×2×16× decoding depth×1 bit.However, since the main symbol and the enhanced symbol are multiplexed,the main symbol may interrupt the state transition of the enhancedsymbol.

FIG. 12 illustrates an interruption of the state transition diagram ofthe enhanced symbol caused by the main symbol. Although the actual mainsymbol interruption occurs in multiples of 4 symbols, the interruptionof only two symbols will be described with reference to FIG. 12 forsimplicity. Herein, the enhanced symbol directly preceding the mainsymbol interruption will be referred to as a first enhanced symbol, andthe enhanced symbol directly following the main symbol interruption willbe referred to as a second enhanced symbol. The bold line shown in FIG.12 describes the paths connected by state 0000 of the second enhancedsymbol. Referring to FIG. 12, the first enhanced symbol includes 8states, which can be connected to each state of the second enhancedsymbol. In other words, each state of the second enhanced symbolincludes 2 branches in accordance with the input X2 bit, and herein, 4states can be connected to each branch. At this point, the enhanced-onlyViterbi decoder should estimate the state transition from the firstenhanced symbol to the second enhanced symbol. Therefore, two differentmethods of dealing with the main symbol interruption from the ACS unitof the enhanced-only Viterbi decoder may be proposed, which will now bedescribed as follows.

In the first method, each of the 8 states that can be connected to eachstate of when performing the ACS operation during the second enhancedsymbol section, without performing the ACS operation during the firstthe main symbol section, is compared to one another, so that the statehaving the minimum metric value can be selected. More specifically,there are two branches in each state during the second enhanced symbol,wherein each branch may be connected to 4 states of the first enhancedsymbol. Accordingly, the state having the minimum metric value among the4 states (i.e., the path metric value of the previous state) isselected, and the selected path metric of the previous state is added tothe branch metric value of the corresponding branch. The added resultbecomes the current path metric value of each branch. At this point,since each state of the second enhanced symbol includes 2 branches, thecurrent metric value of the two branches for each state is compared toone another, so as to select the smallest (or lowest) path metric valueand to store the path metric value of the corresponding state.Thereafter, the survivor of the selected path and the path selectinginformation is outputted to the path history unit.

On the other hand, in the second method, by performing the ACS operationduring the main symbol section, the state transition can be continuouslyestimated during the main symbol section. Although the ACS operation isperformed during the main symbol section, the enhanced-only Viterbidecoder does not store the selected survivor in the path history unitduring the main symbol section. However, the path selecting information,which is obtained by the ACS operation in the main symbol section, isused to exchange the path history of each state at the path historyunit. For example, only the path selecting information, which isobtained by the ACS operation for the main symbol, is outputted to thepath history unit, and the survivor of the selected path may not beoutputted to the path history unit. In another example, the survivor andthe path selecting information that are obtained by the ACS operationresult are all outputted to the path history unit. And, when the symbolinputted from the path history unit is the main symbol, then thesurvivor may not be received and only the path selecting information maybe received. Furthermore, since the path history unit of theenhanced-only Viterbi decoder only operates when the input survivor isthe enhanced symbol, the order of the finally decoded and outputtedsymbol may be different from that of the symbol of the Viterbi decoderinput.

FIG. 13 illustrates the above-described effect in detail. Part (a) ofFIG. 13 shows an input symbol sequence being inputted to any one of the12 Viterbi decoders. Referring to FIG. 13, E represents the enhancedsymbol, M represents the main symbol, and the numeral following E or Mrepresents the time index. Part (b) of FIG. 13 shows a symbol columnbeing finally outputted from an enhanced/main integrated Viterbidecoder, wherein it is known that decoding decision values are outputtedin the same order of the input symbol sequence, after a set portion ofdecoding depth. Finally, part (c) of FIG. 13 shows the output order ofthe decoding decision values of the enhanced-only Viterbi decoder.

As shown in part (c) of FIG. 13, since 8 enhanced symbols should beinputted to the path history unit in order to make a decision for aninput E1 (i.e., decoding depth=8 assumptions), the decision for E1 canbe made when E17 is inputted. In the input terminal of the Viterbidecoder, the symbols are inputted in the order of symbols E1, E2, E3,and E4, then symbols M5, M6, M7, and M8, followed by symbols E9, E10,E11, and E12. Subsequently, in the final output, symbols E1, E2, E3, andE4 and symbols E9, E10, E11, and E12 are outputted consecutively. Thisis because the path history unit of the enhanced-only Viterbi decoder isonly operated when enhanced symbols are inputted. Therefore, thedecoding decision of the enhanced-only Viterbi decoder should bere-ordered to be in the same order as that of the input symbol column.

FIG. 14 illustrates a re-ordering of decoded enhanced symbol outputs.The decoding decision, which is outputted from the path history unit ofeach 12 Viterbi decoders, is serially outputted in a time-divisionmethod. Accordingly, a demultiplexer stores the corresponding decodeddecision value in a first-in first-out (FIFO) unit in accordance with away signal (i.e., signal indicating which of the 12 decoders is beingused). At this point, since the FIFO unit performs buffering only on theenhanced symbol, the demultiplexer operates only during the sectionwhere the E/M flag is high. In addition, a first multiplexer (MUX1) alsooperates only during the section where the E/M flag is high and receivesa way signal, so as to output the output of the corresponding FIFO unit.Referring to FIG. 14, the E/M flag and the way signal used in the firstmultiplexer (MUX1) has a set amount of time delay as compared to thesignals used in the demultiplexer. Meanwhile, an E/M flag used in asecond multiplexer (MUX2) is identical to that of the first multiplexer(MUX1). Also, the second multiplexer (MUX2) multiplexes the output ofthe first multiplexer (MUX1) during the section where the E/M flag ishigh. Alternatively, during the section where the E/M flag is low, thesecond multiplexer (MUX2) either outputs a set of dummy data ormultiplexes and outputs the output of the main-only Viterbi decoder.When the dummy data is multiplexed, the enhanced symbol and the mainsymbol are each outputted through a separate path from the final outputof the Viterbi decoder. On the other hand, when the main symbol ismultiplexed, the decoded result of the enhanced symbol and the mainsymbol is outputted through a single path.

FIG. 15 illustrates an enhanced-only Viterbi decoder according to asecond embodiment of the present invention. A branch metric calculator811 and a polarity inversion estimator 814 of the enhanced-only Viterbidecoder are identical to those of the enhanced/main integrated Viterbidecoder, shown in FIG. 11, and so the description of the same will beomitted for simplicity. Also, the operations of an ACS unit 812 of apositive decoder and an ACS unit 813 of a negative decoder have beendescribed above. In the enhanced-only Viterbi decoder, the survivorbeing outputted to the path history unit includes only one X2 bit.Therefore, the memory capacity required in the path history units 815and 816 is 12×2×16× decoding depth×1 bit. Furthermore, the enhanced-onlyViterbi decoder further includes a re-ordering unit 818 for performingthe re-ordering of the output as described in FIG. and FIG. 14. Sincethe main-only Viterbi decoder is identical to the Viterbi decoder of theconventional ATSC 8T-VSB receiver, the description of the same will beomitted.

The channel equalizing system used in the E8-VSB receiving systemperforms channel equalization by using an 8-level decision. The decisionvalue obtained by using a Viterbi decoding process is more reliable thanthe decision value obtained by using an 8-level slicer. Therefore, inthe present invention, by feeding-back the 8-level decision that isperformed from the Viterbi decoder to the channel equalizing system, thecapacity of channel equalization may be enhanced.

In order to feed-back decision from the ACS unit, a state having theminimum path metric value is identified from the ACS unit of the E8-VSBViterbi decoder. Then, an output level (i.e., one of the 8 levels) of aselected path of the identified state is fed-back to the channelequalizing system. At this point, one of the output levels of each ACSunit of the positive and negative decoders is selected in accordancewith the polarity signal, which is outputted from the polarity inversionestimator of the enhanced symbol. Thereafter, the selected output levelis fed-back to the channel equalizing system. This generally correspondsto the decision feedback of the Viterbi decoder, when the decoding depthis ‘0’.

The reliability of a decision value of the Viterbi decoder may increasein accordance with an increase of the decoding depth to a certainextent. However, the increase of the decoding depth may cause a longertime delay before the decoding decision. When the decoding depth of theViterbi decoder of the E8-VSB receiver increases by 1, the time delay ofthe decision feedback may increase as much as 12 symbols. However, inthe channel equalizing system, when the path history unit feeds-back thedecoding decision for each decoding depth, a decision value having amaximum reliability within a range allowed by the time delay may beobtained and used. Accordingly, when the survivor is outputted from theACS unit of the Viterbi decoder, the output level information (i.e., 3bits including C2C1C0) of a selected path should also be added. Then,the path history unit stores the output level information (i.e., the 3bits C2C1C0) and maintains the history corresponding to the timeequivalent to the decoding depth. Furthermore, the survivor of the statehaving the minimum path metric value is outputted at each trace-backstage, so as to feed-back the outputted survivor to the channelequalizing system.

In the channel equalizing system, the decisions for each of the enhancedsymbol and the main symbol should all be fed-back and the decision delayshould be reduced. Therefore, it is preferable that the feedback isperformed while setting the enhanced/main integrated Viterbi decoder asthe basic decoder. Accordingly, when the survivor is outputted from theACS unit of FIG. 11, the 3 bits C2C1C0 are additionally outputted. Then,the 3 bits C2C1C0 are added to the conventional 2 bits and stored in thepath history unit. Thereafter, the state having the minimum path metricvalue, which is inputted from the ACS unit, is identified, and C2C1C0for each decoding depth are outputted and fed-back through the channelequalizing system. Evidently, the feedback outputted from the positivedecoder and the feedback outputted from the negative decoder should beselected in accordance with the polarity signal of the polarityinversion estimator.

The Viterbi decoder of the E8-VSB receiving system has the followingadvantages. First of all, an enhanced symbol and a main symbol may allbe decoded. When using the enhanced symbol, an enhanced symbol processorand a trellis encoder being concatenated to one another are collectivelydecoded, thereby enhancing the decoding capacity. Moreover, the enhancedsymbol is divided into a ½ enhanced symbol and a ¼ enhanced symbol,which are decoded accordingly. Herein, the decoding of the ¼ enhancedsymbol is more reliable than the decoding of the ½ enhanced symbol.Also, in the present invention, a polarity inversion of the enhancedsymbol can be estimated. Furthermore, an enhanced-only Viterbi decoderis configured in order to minimize the adverse effect that the mainsymbol may cause to the decoding capacity of the enhanced symbol.Finally, an 8-level decision performed at the Viterbi decoder isfed-back to a channel equalizing system, thereby enhancing the channelequalizing capacity.

The terminologies used in the description of the present invention havebeen defined while taking into account the functions of the presentinvention. Such terminologies may vary depending upon the intentions orpractice of those skilled in the art. Therefore, a specific definitionfor each term should be made and given based on the overall descriptionof the present invention.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present inventionwithout departing from the spirit or scope of the inventions. Thus, itis intended that the present invention covers the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A method for processing a digital television(DTV) broadcast signal in a broadcasting receiver, the methodcomprising: receiving, by a tuner, the DTV broadcast signal includingenhanced data; equalizing the received DTV broadcast signal bycompensating channel distortion of the received DTV broadcast signal;decoding signaling information from the equalized DTV broadcast signal,wherein the signaling information includes information indicatingwhether the enhanced data are coded at a ½ code rate or at a ¼ coderate; decoding, by a decoder, the enhanced data included in theequalized DTV broadcast signal; and derandomizing, by a derandomizer,the decoded enhanced data, wherein the enhanced data in the received DTVbroadcast signal are generated in a broadcast transmitter by:randomizing original enhanced data, first Reed Solomon (RS) encoding therandomized original enhanced data, convolutional encoding the firstRS-encoded original enhanced data, second RS encoding the convolutionalencoded original enhanced data, interleaving the second RS-encodedoriginal enhanced data, and trellis encoding the interleaved originalenhanced data.
 2. The method of claim 1, wherein the received DTVbroadcast signal further includes main data that the convolutionalencoding is not performed.
 3. The method of claim 1, wherein theenhanced data is decoded based on the signaling information.
 4. Themethod of claim 1, wherein the received DTV broadcast signal furtherincludes segment synchronization data and field synchronization data. 5.A broadcasting receiver for processing a digital television (DTV)broadcast signal, the broadcasting receiver comprising: a tuner forreceiving the DTV broadcast signal including enhanced data; an equalizerfor equalizing the received DTV broadcast signal by compensating channeldistortion of the received DTV broadcast signal; an information recoveryunit for decoding signaling information from the equalized DTV broadcastsignal, wherein the signaling information includes informationindicating whether the enhanced data are coded at a ½ code rate or at a¼ code rate; a decoder for decoding the enhanced data included in theequalized DTV broadcast signal; and a derandomizer for derandomizing thedecoded enhanced data, wherein the enhanced data in the received DTVbroadcast signal are generated in a broadcast transmitter by:randomizing original enhanced data, first Reed Solomon (RS) encoding therandomized original enhanced data, convolutional encoding the firstRS-encoded original enhanced data, second RS encoding the convolutionalencoded original enhanced data, interleaving the second RS-encodedoriginal enhanced data, and trellis encoding the interleaved originalenhanced data.
 6. The broadcasting receiver of claim 5, wherein thereceived DTV broadcast signal further includes main data that theconvolutional encoding is not performed.
 7. The broadcasting receiver ofclaim 5, wherein the decoder decodes the enhanced data based on thesignaling information.
 8. The broadcasting receiver of claim 5, whereinthe received DTV broadcast signal further includes segmentsynchronization data and field synchronization data.
 9. A method forprocessing a broadcast signal in a broadcasting receiver, the methodcomprising: receiving the broadcast signal including first enhanceddata, second enhanced data and signaling information, wherein the firstenhanced data are encoded at a first code rate and the second enhanceddata are encoded at a second code rate; demodulating the receivedbroadcast signal; decoding the signaling information in the demodulatedbroadcast signal, wherein the decoded signaling information includesinformation for identifying the first enhanced data and the secondenhanced data; decoding the first enhanced data in the demodulatedbroadcast signal based on the decoded signaling information; anddecoding the second enhanced data in the demodulated broadcast signalbased on the decoded signaling information.
 10. The method of claim 9,further comprising: derandomizing the decoded first enhanced data andthe decoded second enhanced data.
 11. The method of claim 9, wherein thebroadcast signal further includes main data multiplexed with the firstand second enhanced data.
 12. The method of claim 11, wherein thedecoded signaling information further includes information foridentifying the main data.
 13. A broadcasting receiver for processing abroadcast signal, the broadcasting receiver comprising: a tuner forreceiving the broadcast signal including first enhanced data, secondenhanced data and signaling information, wherein the first enhanced dataare encoded at a first code rate and the second enhanced data areencoded at a second code rate; a demodulator for demodulating thereceived broadcast signal; a signaling decoder for decoding thesignaling information in the demodulated broadcast signal, wherein thedecoded signaling information includes information for identifying thefirst enhanced data and the second enhanced data; and a decoder fordecoding the first enhanced data in the demodulated broadcast signalbased on the decoded signaling information and decoding the secondenhanced data in the demodulated broadcast signal based on the decodedsignaling information.
 14. The broadcasting receiver of claim 13,further comprising: a derandomizer for derandomizing the decoded firstenhanced data and the decoded second enhanced data.
 15. The broadcastingreceiver of claim 13, wherein the broadcast signal further includes maindata multiplexed with the first and second enhanced data.
 16. Thebroadcasting receiver of claim 15, wherein the decoded signalinginformation further includes information for identifying the main data.